View CD74HCT573M_1225055.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SEMICONDUCTOR
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
High Speed CMOS Logic Octal Transparent Latch, Three-State Output
Description
The Harris CD74HC373, CD74HCT373, CD54HC573, CD74HC573, and CD74HCT573 are high speed Octal Transparent Latches manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL devices. The CD74HCT373 and CD74HCT573 are functionally as well as pin compatible with the standard 74LS373 and 74LS573. The outputs are transparent to the inputs when the latch enable (LE) is high. When the latch enable (LE) goes low the data is latched. The output enable (OE) controls the threestate outputs. When the output enable (OE) is high the outputs are in the high impedance state. The latch operation is independent to the state of the output enable. The 373 and 573 are identical in function and differ only in their pinout arrangements.
November 1997
Features
* Common Latch Enable Control * Common Three-State Output Enable Control * Buffered Inputs * Three-State Outputs * Bus Line Driving Capacity * Typical Propagation Delay = 12ns at VCC = 5V, CL = 15pF, TA = 25oC (Data to Output for HC373) * Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads * Wide Operating Temperature Range . . . -55oC to 125oC * Balanced Propagation Delay and Transition Times * Significant Power Reduction Compared to LSTTL Logic ICs * HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V * HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH
Ordering Information
PART NUMBER CD54HC573F CD74HC373E CD74HCT373E CD74HC573E CD74HCT573E CD74HC373M CD74HCT373M CD74HC573M CD74HCT573M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld PDIP 20 Ld PDIP 20 Ld PDIP 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC 20 Ld SOIC 20 Ld SOIC PKG. NO. F20.3 F20.3 E20.3 E20.3 E20.3 M20.3 M20.3 M20.3 M20.3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1997
File Number
1679.1
1
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573 Pinout
CD74HC373, CD74HCT373 (PDIP, SOIC) TOP VIEW
OE 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 GND 10 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 LE
CD54HC573, CD74HC573, CD74HCT573 (PDIP, SOIC, CERDIP) TOP VIEW
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE
Functional Block Diagrams
CD74HC373, CD74HCT373, CD74HC573, CD74HCT573
D0 D1 D2 D3 D4 D5 D6 D7
D G LE O
D G O
D G
O
D G O
D G O
D G O
D G O
D G O
OE
O0
O1
O2
O3
O4
O5
O6
O7
CD74HCT573
D0 D1 D2 D3 D4 D5 D6 D7
D G LE
O
D G
O
D G
O
D G
O
D G
O
D G
O
D G
O
D G
O
OE
O0
O1
O2
O3
O4
O5
O6
O7
TRUTH TABLE OUTPUT ENABLE L L L L H LATCH ENABLE H H L L X DATA H L l h X OUTPUT H L L H Z
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, Z = High Impedance State, l = Low voltage level one set-up time prior to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA
Thermal Information
Thermal Resistance (Typical, Note 3). . . . JA (oC/W) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 125 N/A CERDIP Package . . . . . . . . . . . . . . . . 85 24 SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current II ICC VCC or GND VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 0 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 80 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 160 V V V V V V V V V V V V V V V V A A SYMBOL VI (V) IO (mA) VCC (V) MIN 25oC TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
3
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
DC Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Three-State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Three-State Leakage Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load (Note 4) NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. II ICC VCC to GND VCC or GND VIL or VIH VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL VI (V) VIL or VIH IO (mA) VCC (V) VO = VCC or GND 6 MIN 25oC TYP MAX 0.5 -40oC TO 85oC MIN MAX 5 -55oC TO 125oC MIN MAX 10 UNITS A
-6 -7.8 0.02
4.5 6 4.5
3.98 5.48 -
-
0.1
3.84 5.34 -
0.1
3.7 5.2 -
0.1
V V V
6 7.8 0 VO = VCC or GND -
4.5 6 5.5 5.5 6
-
-
0.26 0.26 0.1 8 0.5
-
0.33 0.33 1 80 5
-
0.4 0.4 1 160 10
V V A A A
ICC
4.5 to 5.5
-
100
360
-
450
-
490
A
HCT Input Loading Table
UNIT LOADS INPUT OE Dn LE HCT373 1.5 0.4 0.6 HCT573 1.25 0.3 0.65
NOTE: Unit Load is ICC limit specified in DC Electrical Specifications table, e.g., 360A max at 25oC.
4
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Prerequisite For Switching Specifications
PARAMETER HC TYPES LE Pulse Width tW 2 4.5 6 Set-up Time Data to LE tSU 2 4.5 6 Hold Time, Data to LE (573) tH 2 4.5 6 Hold Time, Data to LE (373) tH 2 4.5 6 HCT TYPES LE Pulse Width Set-up Time Data to LE Hold Time, Data to LE tw tw tH Input tr, tf = 6ns 25oC VCC (V) TYP MAX -40oC TO 85oC MAX -55oC TO 125oC MAX UNITS 4.5 4.5 4.5 16 13 10 20 16 13 24 20 15 ns ns ns 80 16 14 50 10 9 40 8 7 5 5 5 100 20 17 65 13 11 50 10 9 5 5 5 120 24 20 75 15 13 60 12 10 5 5 5 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TEST CONDITIONS VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS
Switching Specifications
PARAMETER HC TYPES Propagation Delay, Data to Qn (HC/HCT373)
SYMBOL
TEST CONDITIONS
tPLH, tPHL
CL = 50pF
2 4.5 6
12 14 14 12
150 30 26 175 35 30 175 35 30 150 30 26 -
190 38 33 220 44 37 220 44 37 190 38 33 -
225 45 38 265 53 45 265 53 45 225 45 38 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CL = 15pF Propagation Delay, Data to Qn (HC/HCT573) tPLH, tPHL CL = 50pF
5 2 4.5 6
CL = 15pF Propagation Delay, LE to Qn tPLH, tPHL CL = 50pF
5 2 4.5 6
CL = 15pF Output Enabling Time tPZL, tPZH CL = 50pF
5 2 4.5 6
CL = 15pF
5
5
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Switching Specifications
Input tr, tf = 6ns (Continued) 25oC VCC (V) 2 4.5 6 CL = 15pF Output Transition Time tTLH, tTHL CL = 50pF 5 2 4.5 6 Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Propagation Delay, Data to Qn (HC/HCT373) Propagation Delay, Data to Qn (HC/HCT573) Propagation Delay, LE to Qn Output Enabling Time tPLH, tPHL CL = 50pF CL = 15pF tPLH, tPHL CL = 50pF CL = 15pF tPLH, tPHL CL = 50pF CL = 15pF tPZL, tPZH CL = 50pF CL = 15pF Output Disabling Time tPLZ, tPZH CL = 50pF CL = 15pF Output Transition Time Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 5, 6) NOTES: 5. CPD is used to determine the no-load dynamic power consumption, per latch. 6. PD (total power per latch) = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. tTLH, tTHL CI CO CPD CL = 50pF 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 13 17 14 14 14 53 32 35 35 35 35 12 10 20 40 44 44 44 44 15 10 20 48 53 53 53 53 18 10 20 ns ns ns ns ns ns ns ns ns ns ns pF pF pF CI CO CPD 5 TYP 12 51 MAX 150 30 26 60 12 10 10 20 -40oC TO 85oC MAX 190 38 33 75 15 13 10 20 -55oC TO 125oC MAX 225 45 38 90 18 15 10 20 UNITS ns ns ns ns ns ns ns pF pF pF
PARAMETER Output Disabling Time
SYMBOL tPLZ, tPHZ
TEST CONDITIONS CL = 50pF
6
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573 Test Circuits and Waveforms
trCL CLOCK 90% 10% tfCL tWL + tWH = I fCL VCC 50% 10% tWL 50% 50% GND tWH CLOCK trCL = 6ns tWL + tWH = tfCL = 6ns 2.7V 0.3V I fCL 3V 1.3V 0.3V tWL 1.3V 1.3V GND tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH
tr = 6ns INPUT 90% 50% 10%
tf = 6ns VCC
tr = 6ns INPUT GND 2.7V 1.3V 0.3V
tf = 6ns 3V
GND tTLH 90%
tTHL
tTLH 90% 50% 10% tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V 10%
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
trCL CLOCK INPUT 90% 10% tH(H)
tfCL VCC 50% GND tH(L) VCC DATA INPUT tSU(H) CLOCK INPUT
trCL 2.7V 0.3V tH(H)
tfCL 3V 1.3V GND tH(L) 3V 1.3V 1.3V 1.3V tSU(L) tTLH tTHL 90% 1.3V 10% tPHL GND
DATA INPUT tSU(H) tTLH 90% OUTPUT tPLH tREM VCC SET, RESET OR PRESET tSU(L) tTHL 90% 50% 10% tPHL
50% GND
OUTPUT
90% 1.3V tPLH
50% GND
tREM 3V SET, RESET OR PRESET
1.3V GND
IC
CL 50pF
IC
CL 50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573 Test Circuits and Waveforms
6ns OUTPUT DISABLE 90% 50% 10% tPZL 50% 10% tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED tPZH OUTPUT HIGH TO OFF OUTPUTS ENABLED OUTPUT LOW TO OFF tPHZ 90%
(Continued)
tr VCC GND tPLZ OUTPUT DISABLE 6ns tf 2.7 1.3 6ns 3V 0.3 tPZL GND
6ns
tPLZ OUTPUT LOW TO OFF
10% tPZH
1.3V
1.3V OUTPUTS DISABLED OUTPUTS ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM
OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE
IC WITH THREESTATE OUTPUT
OUTPUT RL = 1k CL 50pF
VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
Sales Office Headquarters
For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS NORTH AMERICA Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Harris Semiconductor PTE Ltd. No. 1 Tannery Road Cencon 1, #09-01 Singapore 1334 TEL: (65) 748-4200 FAX: (65) 748-0400
SEMICONDUCTOR
8

▲Up To Search▲

Price & Availability of CD74HCT573M

	To Download CD74HCT573M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .